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ds07-12522-2e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89140 series mb89145/146 and MB89P147/pv140 n description the mb89140 series is a line of single-chip microcontrollers that use the f 2 mc*-8l cpu core which can operate at low voltage but at high speed. the mb89140 series contains a variety of peripheral functions, such as timers, a serial interface, an a/d converter, and an external interrupt. the mb89140 series is applicable to a wide range of applications from welfare products to industrial equipment, including portable devices. *: f 2 mc stands for fujitsu flexible microcontroller. n features minimum execution time: 0.5 m s/8-mhz oscillation ? 2 mc-8l family cpu core instruction set optimized for controllers (continued) n package multiplication and division instructions 16-bit arithmetic operations test and branch instructions bit manipulation instructions, etc. 64-pin plastic sh-dip 64-pin plastic qfp 64-pin ceramic mdip 64-pin ceramic mqfp (dip-64p-m01) (fpt-64p-m06) (mdp-64c-p02) (mqp-64c-p01)
2 mb89140 series (continued) low-voltage operation (when an a/d converter is not used) low current consumption (compatible with dual-clock system) high-voltage ports on chip five types of timers 8-bit pwm timer (also usable as a reload timer) 12-bit mpg timer (also usable as a ppg output, pwm output, and reload timer) 8/16-bit timer (also usable as two 8-bit timers) 21-bit time-base timer one serial interface swichable transfer direction allows communication with various equipment. 10-bit a/d converter: 12 channels successive approximation type external interrupt: 2 channels two channels are independent and capable of wake-up from low-power consumption modes. (rising edge, falling edge/both edges selectability) ?.3 v to +7.0 v can be applied to int1 (n-ch open-drain) low-power consumption modes stop mode (oscillation stops to minimize the current consumption.) sleep mode (the cpu stops to reduce the current consumption to approx. 1/3 of normal.) subclock mode watch mode reset output and power-on reset selectability
3 mb89140 series n product lineup (continued) mb89145 mb89146 MB89P147 mb89pv140 classi?ation mass production products (mask rom products) one-time prom/ eprom product piggyback/ evaluation product (for evaluation and development) rom size 16 k 8 bits (internal mask rom) 24 k 8 bits (internal mask rom) 32 k 8 bits (internal prom) 32 k 8 bits (external rom) ram size 512 8 bits 768 8 bits 1 k 8 bits cpu functions number of instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, 16 bits minimum execution time: 0.5 m s/8 mhz to 8.0 m s/8 mhz, 61 m s/32.768 khz interrupt processing time: 4.5 m s/8 mhz to 72.0 m s/8 mhz, 562.5 m s/32.768 khz note: the above times change according to the gear function. ports high-voltage output port (p-ch open-drain): 8 (p60 to p67, for heavy current) 16 (p40 to p47, p50 to p57 for low current) buzzer output (p-ch open-drain, high-voltage): 1 (heavy current) output ports (cmos): 4 (p20 to p23) input ports (cmos): 2 (p70 and p71, function as x0a and xia pins when dual-clock system is used.) i/o ports (cmos): 23 (p00 to p07, p10 to p17, p30, and p32 to p37) i/o ports (n-ch open-drain): 1 (p31) total: 55 clock timer 21 bits 1 (in main clock mode), 15 bits 1 (at 32.768 khz) 8-bit pwm timer (timer 1) 8-bit timer operation (toggled output capable, operating clock: 1, 2, 8, 16 system clock cycles) 8-bit resolution pwm operation (conversion cycle: 128 m s to 2.0 ms at 8.0-mhz oscillation, and highest gear speed) 12-bit mpg (timer 4) 12-bit resolution pwm operation (maximum conversion cycle of 2048.4 m s to 16.4 ms at 8.0 mhz-oscillation, and highest gear speed) 12-bit resolution reload timer operation (toggled output capable) 12-bit resolution ppg operation (minimum resolution of 0.5 m s at 8.0-mhz oscillation, and highest gear speed) 8/16-bit timer counter (timer 2, 3) 8/16-bit timer operation (operating clock, internal clock, external trigger) 8/16-bit event counter operation (rising edge/falling edge/both edges selectability) parameter part number
4 mb89140 series (continued) * : varies with conditions such as the operating frequency. (see section n electrical characteristics.? n package and corresponding products : available : not available note: for more information about each package, see section n package dimensions. mb89145 mb89146 MB89P147 mb89pv140 8-bit serial i/o 8 bits lsb first/msb first selectability one clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 4, 8, 16 system clock cycles) 10-bit a/d converter 10-bit resolution 12 channels a/d conversion mode (conversion time of 16.5 m s/8 mhz, and highest gear speed) sense mode (conversion time of 9.0 m s/8 mhz, and highest gear speed) external activation capable external interrupt 2 independent channels (edge selection, interrupt vector, source flag) rising edge/falling edge/both edges selectability built-in analog noise canceller used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.) standby mode sleep mode, stop mode, watch mode, and subclock mode process cmos operating voltage* 2.7 v to 6.0 v eprom for use mbm27c256a-20tv mbm27c256a-20cz package mb89145 mb89146 MB89P147 mb89pv140 dip-64p-m01 dip-64c-a06 fpt-64p-m06 mdp-64c-p02 mqp-64c-p01 parameter part number
5 mb89140 series n differences among products 1. memory size before evaluating using the piggyback product, verify its differences from the product that will actually be used. take particular care on the following points: on the MB89P147, the program area starts from address 8007 h but on the mb89pv140 starts from 8000 h . (on the MB89P147, addresses 8000 h to 8006 h comprise the option setting area, option settings can be read by reading these addresses. on the mb89pv140, addresses 8000 h to 8006 h could also be used as a program rom. however, do not use these addresses in order to maintain compatibility of the MB89P147.) the stack area, etc., is set at the upper limit of the ram. 2. current consumption in the case of the mb89pv140, add the current consumed by the eprom which is connected to the top socket. when operated at low speed, the product with an otprom (one-time prom) or an eprom will consume more current than the product with a mask rom. however, the current consumption in sleep/stop modes is the same. (for more information, see section n electrical characteristics.? 3. mask options functions that can be selected as options and how to designate these options vary by the product. before using options check section n mask options. take particular care on the following points: options are ?ed on the mb89pv140. on the MB89P147, mb89145, and mb89146, the pull-down resistor option can either be selected for all affected pins, or for no pin; it is not possible to specify the pull-down resistor option for individual pins. 4. subclock oscillation feedback resistor a built-in oscillation feedback resistor is provided for the subclock oscillator pin on the mb89pv140, but it is not provided for the mb89145, mb89146, MB89P147. therefor these products should be connected to an external oscillation feedback resistor.
6 mb89140 series n pin assignment (dip-64p-m01) (mdp-64c-p02) (top view) 65 a15/v pp 66 a12 67 a7 68 a6 69 a5 70 a4 71 a3 72 a2 73 a1 74 a0 75 o1 76 o2 77 o3 78 v ss v cc 92 a14 91 a13 90 a8 89 a9 88 a11 87 oe 86 a10 85 ce 84 o8 83 o7 82 o6 81 o5 80 o4 79 1 bz 2 p67 3 p66 4 p65 5 p64 6 p63 7 p62 8 p61 9 p60 10 vfdp 11 p57 12 p56 13 p55 14 p53 15 p50 16 p47 17 p46 18 p45 19 p44 20 p43 21 p42 22 p41 23 p40 24 p23/wdg 25 rst 26 moda 27 x0 28 x1 29 v ss v cc 64 av cc 63 av ss 62 p00/an0 61 p01/an1 60 p02/an2 59 p03/an3 58 p04/an4 57 p05/an5 56 p06/an6 55 p07/an7 54 p10/an8 53 p11/an9 52 p12/ana 51 p13/anb 50 p14 49 p15 48 p16 47 p17/adst 46 p30/int0/trg 45 p31/int1 44 p32/sck 43 p33/so 42 p34/si 41 p35/ec 40 p36/pwo1 39 p37/dtt1 38 p20 37 p21/pwo0 36 30 31 32 p22 35 p70/x0a* 34 p71/x1a* 33 p54 p52 p51 each pin inside the dashed line is for the mb89pv140 only. *: when dual-clock system is selected.
7 mb89140 series pin assignment on package top (mb89pv140 only) n.c.: internally connected. do not use. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 65 n.c. 73 a2 81 n.c. 89 oe 66 a15/v pp 74 a1 82 o4 90 n.c. 67 a12 75 a0 83 o5 91 a11 68 a7 76 n.c. 84 o6 92 a9 69 a6 77 o1 85 o7 93 a8 70 a5 78 o2 86 o8 94 a13 71 a4 79 o3 87 ce 95 a14 72 a3 80 v ss 88 a10 96 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p61 p60 vfdp p57 p56 p55 p54 p53 p52 p51 p50 p47 p46 p45 p44 p43 p42 p41 p40 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p03/an3 p04/an4 p05/an5 p06/an6 p07/an7 p10/an8 p11/an9 p12/ana p13/anb p14 p15 p16 p17/adst p30/int0/trg p31/int1 p32/sck p33/so p34/si p35/ec 64 63 62 61 60 59 58 57 56 55 54 53 52 p62 p63 p64 p65 p66 p67 bz v cc av cc av ss p00/an0 p01/an1 p02/an2 20 21 22 23 24 25 26 27 28 29 30 31 32 p23/wdg rst moda x0 x1 v ss p71/x1a* p70/x0a* p22 p21/pwo0 p20 p37/dtti p36/pwo1 85 86 87 88 89 90 91 92 93 77 76 75 74 73 72 71 70 69 84 83 82 81 80 79 78 94 95 96 65 66 67 68 (top view) (fpt-64p-m06) (mqp-64c-p01) each pin inside the dashed line is for the mb89pv140 only. *: when dual-clock system is selected.
8 mb89140 series n pin description (continued) *1: dip-64p-m01 *2: mdp-64c-p02 *3: fpt-64p-m06 *4: mqp-64c-p01 pin no. pin name circuit type function sdip *1 mdip *2 qfp *3 mqfp *4 30 23 x0 a main clock crystal oscillator pins 31 24 x1 29 22 moda c operating mode selection pin connect directly to v ss in normal operation. this pin functions as the v pp pin in eprom products. 28 21 rst d reset i/o pin this pin is an n-ch open-drain output type with a pull-up resistor, and a hysteresis input type. ? is output from this pin by an internal reset source when the option is set. the internal circuit is initialized by the input of ?? this pin is with a noise canceller. 54 to 61 47 to 54 p07/an7 to p00/an0 g general-purpose i/o ports the input is a hysteresis input type and with a built-in noise canceller. although these ports also serve as an analog input, analog input does not pass through the hysteresis input noise canceller. 46 39 p17/adst j general-purpose i/o port the input is a hysteresis input type and with a built-in noise canceller. also serves as an a/d converter external activation. 47 to 49 40 to 42 p16 to p14 j general-purpose i/o ports the input is a hysteresis input type and with a built-in noise canceller. 50 to 53 43 to 46 p13/anb to p10/an8 g general-purpose i/o ports the input is a hysteresis input type and with a built-in noise canceller. although these ports also serves as an analog input, analog input does not pass through the hysteresis input noise canceller. 34, 33 27, 26 p70/x0a, p71/x1a b/k general-purpose i/o ports with a built-in noise canceller (single-clock operation) function as subclock crystal oscillator pins. (dual-clock operation) 35 28 p22 e general-purpose output port 27 20 p23/wdg e general-purpose output port also serves as a watchdog output. 36 29 p21/pwo0 e general-purpose output port also serves as the pwm output for the 8-bit pwm timer. 37 30 p20 e general-purpose output port
9 mb89140 series (continued) *1: dip-64p-m01 *2: mdp-64c-p02 *3: fpt-64p-m06 *4: mqp-64c-p01 pin no. pin name circuit type function sdip *1 mdip *2 qfp *3 mqfp *4 38 31 p37/dtti j general-purpose i/o port the input is a hysteresis input type and with a built-in noise canceller. when overcurrent is detected, the 12- bit mpg output can be inactivated by the external edge input. 39 32 p36/pwo1 j general-purpose i/o port the input is a hysteresis input type and with a built-in noise canceller. also serves as a 12-bit mpg output. 40 33 p35/ec j general-purpose i/o port the input is a hysteresis input type and with a built-in noise canceller. also serves as the external clock input for the 8/16-bit timer/counter. 41 34 p34/si j general-purpose i/o port the input is a hysteresis input type and with a built-in noise canceller. also serves as the serial data input for the 8-bit serial interface. 42 35 p33/so j general-purpose i/o port the input is a hysteresis input type and with a built-in noise canceller. also serves as the serial data output for the 8-bit serial interface. 43 36 p32/sck j general-purpose i/o port the input is a hysteresis input type and with a built-in noise canceller. also serves as the serial transfer clock for the 8-bit serial interface. 44 37 p31/int1 f general-purpose i/o port the output is an n-ch open-drain type. the input is a hysteresis input type and with a built-in noise canceller. also serves as an external interrupt. the interrupt input is also a hysteresis input type and with a built-in noise canceller. 45 38 p30/int0/trg j general-purpose i/o port the input is a hysteresis input type and with a built-in noise canceller. also serve as an external interrupt or as an mpg trigger input. the interrupt input is also a hysteresis input type and with a built-in noise canceller. 1 58 bz i buzzer output-only pin p-ch high-voltage open-drain output port 19 to 26, 11 to 18 12 to 19, 4 to 11 p47 to p40, p57 to p50 h low-current p-ch high-voltage open-drain output ports products with and without a built-in pull-down resistor between these pins and the vfdp pin are provided.
10 mb89140 series (continued) *1: dip-64p-m01 *2: mdp-64c-p02 *3: fpt-64p-m06 *4: mqp-64c-p01 pin no. pin name circuit type function sdip *1 mdip *2 qfp *3 mqfp *4 2 to 9 59 to 64 1, 2 p67 to p60 h heavy-current p-ch high-voltage open-drain output port products with and without a built-in pull-down resistor between these pins and the vfdp pin are provided. 10 3 vfdp voltage supply pin for connection to a pull-down resistor for ports 4, 5, and 6. in products without a built-in pull-down resistor and in the mb89pv140, this pin should be left open. 64 57 v cc power supply pin 32 25 v ss power supply (gnd) pin 63 56 av cc a/d converter power supply pin use this pin at the same voltage as v cc . 62 55 av ss a/d converter power supply (gnd) pin use this pin at the same voltage as v ss .
11 mb89140 series external eprom pins (mb89pv140 only) *1: dip-64p-m01 *2: mdp-64c-p02 *3: fpt-64p-m06 *4: mqp-64c-p01 pin no. pin name i/o function sdip *3 mdip *4 qfp *1 mqfp *2 65 66 a15/v pp o ? level output pin 66 67 68 69 70 71 72 73 74 67 68 69 70 71 72 73 74 75 a12 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins 75 76 77 77 78 79 o1 o2 o3 i data input pins 78 80 v ss o power supply (gnd) pin 79 80 81 82 83 82 83 84 85 86 o4 o5 o6 o7 o8 i data input pins 84 87 ce o rom chip enable pin outputs ? during standby. 85 88 a10 o address output pin 86 89 oe o rom output enable pin outputs ? at all times. 87 88 89 91 92 93 a11 a9 a8 o address output pins 90 94 a13 91 95 a14 92 96 v cc o eprom power supply pin 65 76 81 90 n.c. internally connected pins be sure to leave them open.
12 mb89140 series n i/o circuit type (continued) type circuit remarks a crystal or ceramic oscillation type (main clock) at an oscillation feedback resistor of approximately 1 m w /5.0 v b crystal or ceramic oscillation type (subclock) at an oscillation feedback resistor of approximately 4.5 m w /5.0 v (the built-in feedback resistor is not provided except on the mb89pv140-102.) c d at an output pull-up resistor (p-ch) of approximately 50 k w /5.0 v cmos hysteresis input (with noise canceller) e cmos output f n-ch open-drain output cmos hysteresis input (with noise canceller) x1 x0 standby control signal x1a standby control signal x0a r p-ch n-ch hysteresis input (with noise canceller) p-ch n-ch n-ch hysteresis input (with noise canceller)
13 mb89140 series (continued) type circuit remarks g cmos output cmos hysteresis input (with noise canceller, except analog input) h p-ch high-voltage open-drain output products with and without a built-in pull-down resistor are provided (except the mb89pv140). i p-ch high-voltage open-drain output j cmos output cmos hysteresis input (with noise canceller) pull-up resistor optional k cmos hysteresis input (with noise canceller) p-ch n-ch hysteresis input (with noise canceller) port analog input p-ch vfdp p-ch p-ch n-ch hysteresis input (with noise canceller) port hysteresis input (with noise canceller) port
14 mb89140 series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on ?. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . (however, up to 7.0 v can be applied to p31/int pin, regardless of v cc ) when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 4. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid ?ctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple ?ctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient ?ctuation rate will be less than 0.1 v/ms at the time of a momentary ?ctuation such as when power is switched. 5. precautions when using an external clock even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.
15 mb89140 series n programming to the eprom on the MB89P147 the MB89P147 is an otprom version of the mb89140 series. 1. features 32-kbyte prom on chip options can be set using the eprom programmer. equivalency to the mbm27c256a in eprom mode (when programmed with the eprom programmer) 2. memory space memory space in each mode such as 32-kbyte prom, option area is diagrammed below. 3. programming to the eprom in eprom mode, the MB89P147 functions equivalent to the mbm27c256a. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. when the operating rom area for a single chip is 32 kbytes (8007 h to ffff h ) the prom can be programmed as follows: programming procedure (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0007 h to 7fff h (note that addresses 8007 h to ffff h while operating as a single chip assign to 0007 h to 7fff h in eprom mode). load option data into addresses 0000 h to 0006 h of the eprom programmer. (for information about each corresponding option, see ?. setting otprom options. in section n programming to the eprom with piggyback/evaluation device ) (3) program to 0000 h to 7fff h with the eprom programmer. prom 32 kb ffff h 0000 h 8000 h 0080 h 0480 h not available single chip address eprom mode (corresponding addresses on the eprom programmer) i/o ram 8007 h not available 7fff h 0000 h 0007 h eprom 32 kb option area
16 mb89140 series 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. 5. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 6. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 package compatible socket adapter dip-64p-m01 rom-64sd-28dp-8l4 fpt-64p-m06 rom-64qf-28dp-8l4 program, verify aging +150?, 48 hrs. data verification assembly
17 mb89140 series n programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c256a-20tv, mbm27c256a-20cz 2. programming socket adapter to program to the prom using an eprom programmer, use the socket adapter (manufacturer: sun hayato co., ltd.) listed below. inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 3. memory space memory space in each mode, such as 32-kbyte prom, option area is diagrammed below. 4. programming to the eprom (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0007 h to 7fff h . (3) program to 0000 h to 7fff h with the eprom programmer. package adapter socket part number lcc-32 (rectangle) rom-32lc-28dp-yg lcc-32 (square) rom-32lc-28dp-s prom 32 kb ffff h 0000 h 8000 h 0080 h 0480 h not available single chip address corresponding addresses on the eprom programmer i/o ram 8007 h not available 7fff h 0000 h 0007 h eprom 32 kb option area
18 mb89140 series 5. setting otprom options the programming procedure is the same as that for the prom. options can be set by programming values at the addresses shown on the memory map. the relationship between bits and options is shown on the following bit map: otprom option bit map notes: set each bit to 1 to erase. do not write 0 to the vacant bit. the read value of the vacant bit is 1, unless 0 is written to it. the parenthesized addresses are the corresponding addresses on the eprom programmer. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 8000 h (0000 h ) vacancy readable and writable vacancy readable and writable vacancy readable and writable single/dual- clock system 1: dual clock 0: single clock reset pin output 1: yes 0: no power-on reset 1: yes 0: no reserved (write 1 bit to this bit.) reserved (write 1 bit to this bit.) 8001 h (0001 h ) p17 pull-up 1: no 0: yes p16 pull-up 1: no 0: yes p15 pull-up 1: no 0: yes p14 pull-up 1: no 0: yes vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable 8002 h (0002 h ) p37 pull-up 1: no 0: yes p36 pull-up 1: no 0: yes p35 pull-up 1: no 0: yes p34 pull-up 1: no 0: yes p33 pull-up 1: no 0: yes p32 pull-up 1: no 0: yes vacancy readable and writable vacancy readable and writable 8003 h (0003 h ) vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable 8004 h (0004 h ) vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable 8005 h (0005 h ) vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable 8006 h (0006 h ) vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable
19 mb89140 series n block diagram x0 x1 main clock oscillator p70, p71 clock controller subclock oscillator (32.768 khz) cmos input port ram f 2 mc-8l cpu rom v cc , v ss other pins time-base timer 8-bit serial interface p35/ec p32/sck p60 to p67 bz x1a 8-bit pwm timer mode control 10-bit a/d converter cmos i/o port p17/adst p14 to p16 p13/anb to p10/an8 p07/an7 to p00/an0 av cc av ss high-voltage port 6 12-bit mpg 8/16-bit timer/counter p31/int1 (n-ch open-drain) cmos i/o port x0a cmos output port p23/wdg p22 p20 p21/pwo0 moda 4 4 8 buzzer p50 to p57 high-voltage port 5 p40 to p47 high-voltage port 4 external interrupt vfdp p30/trg/int0 reset circuit rst p33/so p34/si p37/dtti p36/pwo1 port 7 port 2 port 3 internal bus port 0 and port 1 8 8 8
20 mb89140 series n cpu core 1. memory space the microcontrollers of the mb89140 series offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located at the lowest address. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89140 series is structured as illustrated below. memory space 0000 h 0080 h 0100 h 0480 h 8000 h 8006 h i/o ram register not available external rom 32 kb ffff h ffff h mb89pv140 0200 h mb89145 mb89146 MB89P147 ffff h ffff h * 0000 h 0080 h 0100 h c000 h i/o ram register not available rom 16 kb 0200 h 0000 h 0080 h 0100 h 0380 h i/o ram register not available rom 24 kb 0200 h 0000 h 0080 h 0100 h 0480 h 8000 h i/o ram register not available prom 32 kb 0200 h * 0280 h a000 h 8006 h since addresses 8000 h to 8005 h for the MB89P147 comprise an option area, do not use this area for the mb89pv140. *:
21 mb89140 series 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modi?ation extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h undefined undefined undefined undefined undefined i-flag = 0, il1, 0 = 11 other bits are undefined. initial value structure of the program status register vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
22 mb89140 series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-?g: set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared otherwise. this ?g is for decimal adjustment instructions. i-?g: interrupt is allowed when this ?g is set to 1. interrupt is prohibited when the ?g is set to 0. set to 0 when reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-?g: set if the msb is set to 1 as the result of an arithmetic operation. cleared when the bit is set to 0. z-?g: set when an arithmetic operation results in 0. cleared otherwise. v-?g: set if the complement on 2 over?ws as a result of an arithmetic operation. reset if the over?w does not occur. c-?g: set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low = no interrupt 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ?? a15 ?? a14 ?? a13 ?? a12 ?? a11 ?? a10 ?? a9 ?? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 rp generated addresses lower op codes
23 mb89140 series the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers and up to a total of 32 banks can be used in the mb89140 series. the bank currently in use is indicated by the register bank pointer (rp). register bank con?uration this address = 0100 h + 8 (rp) memory area 32 banks r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7
24 mb89140 series n i/o map (continued) address read/write register name register description 00 h (r/w) pdr0 port 0 data register 01 h (w) ddr0 port 0 data direction register 02 h (r/w) pdr1 port 1 data register 03 h (w) ddr1 port 1 data direction register 04 h (r/w) pdr2 port 2 data register 05 h vacancy 06 h vacancy 07 h (r/w) sycc system clock control register 08 h (r/w) stbc standby control register 09 h (r/w) wdtc watchdog timer control register 0a h (r/w) tbcr time-base timer control register 0b h (r/w) wpcr watch prescaler control register 0c h (r/w) pdr3 port 3 data register 0d h (w) ddr3 port 3 data direction register 0e h (r/w) buzr buzzer register 0f h (r/w) eic external interrupt control register 10 h (r/w) pdr4 port 4 data register 11 h (r/w) pdr5 port 5 data register 12 h (r/w) pdr6 port 6 data register 13 h (r) pdr7 port 7 data register 14 h vacancy 15 h vacancy 16 h (w) comr 8-bit pwm timer compare register 17 h (r/w) cntr 8-bit pwm timer control register 18 h (r/w) t3cr timer 3 control register 19 h (r/w) t2cr timer 2 control register 1a h (r/w) t3dr timer 3 data register 1b h (r/w) t2dr timer 2 data register 1c h (r/w) smr serial mode register 1d h (r/w) sdr serial data register 1e h (r/w) adc1 a/d converter control register 1 1f h (r/w) adc2 a/d converter control register 2
25 mb89140 series (continued) note: do not use vacancies. address read/write register name register description 20 h (r/w) addh a/d converter data register (h) 21 h (r/w) addl a/d converter data register (l) 22 h (w) pcr0 port input control register 0 23 h (w) pcr1 port input control register 1 24 h (r/w) mcnt mpg control register 25 h (r/w) intstr mpg interrupt status register 26 h (w) cmclbr (h) mpg compare clear buffer register h 27 h (w) cmclbr (l) mpg compare clear buffer register l 28 h (w) outcbr (h) mpg output buffer register h 29 h (w) outcbr (l) mpg output buffer register l 2a h vacancy 2b h vacancy 2c h vacancy 2d h vacancy 2e h vacancy 2f h vacancy 30 h to 77 h vacancy 78 h vacancy 79 h vacancy 7a h vacancy 7b h vacancy 7c h (w) ilr1 interrupt level setting register 1 7d h (w) ilr2 interrupt level setting register 2 7e h (w) ilr3 interrupt level setting register 3 7f h vacancy
26 mb89140 series n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) *1: the total average output current is de?ed as the average current that ?ws through all of the relevant pins in a 100 ms period. the output peak current is de?ed as the peak value of any one of the relevant pins. the average output current is de?ed as the average current that ?ws through any one of the relevant pins in a 100 ms period. *2: use av cc and v cc set at the same voltage. take care so that av cc does not exceed v cc , such as when power is turned on. precautions: permanent device damage may occur if the above ?bsolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit remarks min. max. power supply voltage v cc v ss ?0.3 v ss + 7.0 v av cc v ss ?0.3 v ss + 7.0 v *2 i/o voltage v io1 v ss ?0.3 v cc + 0.3 v except p31 v io2 v ss ?0.3 7 v p31 ? level total average output current i oh ?20 ma average value (operating current operating rate) ? level maximum output current i oh ?2 ma p00 to p07, p10 to p17, p20 to p23, p30, p32 to p37 ?0 ma p40 to p47, p50 to p57 ?6 ma p60 to p67, bz ? level average output current i ohav ? ma p00 to p07, p10 to p17, p20 to p23, p30, p32 to p37 average value (operating current operating rate) *1 ?0 ma p40 to p47, p50 to p57 average value (operating current operating rate) *1 ?8 ma p60 to p67, bz average value (operating current operating rate) *1 ? level total average output current i olav 150 ma average value (operating current operating rate) *1 ? level maximum output current i ol 12 ma p00 to p07, p10 to p17, p20 to p23, p30 to p37 ? level average output current i olav 6ma p00 to p07, p10 to p17, p20 to p23, p30 to p37 average value (operating current operating rate) *1 power consumption p d 500 mw operating temperature t a ?0 +85 c storage temperature tstg ?5 +150 c
27 mb89140 series 2. recommended operating conditions ( av ss = v ss = 0.0 v) * : these values vary with the operating frequency and analog assurance range. see figure 1 and ?. a/d converter electrical characteristics. figure 1 operating voltage vs. main clock operating frequency figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/f ch . since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. parameter symbol value unit remarks min. max. power supply voltage v cc av cc 2.7* 6.0* v normal operation assurance range* 2.2 6.0 v in watch mode or subclock operation (only for the MB89P147, the minimum value is 2.7 v.) 1.5 6.0 v retains the ram state in stop mode vfdp v cc ?40 v cc + 0.3 v operating temperature t a ?0 +85 c 1 2 3 4 5 6 2 6 main clock operating frequency (at an instruction cycle of 4/f ch ) (mhz) 345 78 2.0 minimum execution time (instruction cycle) (?) 0.8 0.5 operating voltage (v) operation assurance range
28 mb89140 series 3. dc characteristics ( av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) (continued) parameter symbol pin condition value unit remarks min. typ. max. ? level input voltage v ihs p00 to p07, p10 to p17, p30 to p37, p70, p71, x0, x1, rst , moda 0.7 v cc v cc + 0.3 v hysteresis input ? level input voltage v ils p00 to p07, p10 to p17, p30 to p37, p70, p71, x0, x1, rst , moda v ss ?0.3 0.2 v cc v hysteresis input ? level output voltage v oh1 p00 to p07, p10 to p17, p20 to p23, p30, p32 to p37 i oh = ?.0 ma 2.4 v v oh2 p40 to p47, p50 to p57 i oh = ?0 ma 3.0 v v oh3 p60 to p67, bz i oh = ?8 ma 3.0 v ? level output voltage v ol1 p00 to p07, p10 to p17, p20 to p23, p30, p32 to p37 i ol = 1.8 ma 0.4 v v ol2 rst i ol = 4.0 ma 0.6 v input leakage current i li1 p00 to p07, p10 to p17, p30 to p37, p70, p71, moda 0.45 v < v i < v cc 5 m a without pull-up resistor for p14 to p17 and p32 to p37 i li2 p14 to p17, p32 to p37 v i = 0.0 v ?00 ?00 ?0 m a with pull-up resistor output leakage current i lo1 p40 to p47, p50 to p57 v i = vfdp = v cc ?40 v ?0 m a i lo2 p60 to p67, bz v i = vfdp = v cc ?40 v ?0 m a pull-up resistance r pulu rst p14 to p17, p32 to p37 v i = 0.0 v 25 50 100 k w with pull-up resistor pull-down resistance r puld p40 to p47, p50 to p57, p60 to p67 v oh = 5.0 v 50 100 150 k w with pull-down resistor optional
29 mb89140 series (continued) ( av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) *1: the power supply current is measured at the external clock. *2: for information on t inst , see ?4) instruction cycle in ?. ac characteristics. note: f ch indicates the main clock oscillation frequency. when f ch = 8 mhz, the 4/f ch execution time is 0.5 m s, and the 64/f ch execution time is 8 m s. parameter symbol pin condition value unit remarks min. typ. max. power supply current *1 i cc1 v cc f ch = 8 mhz v cc = 5.0 v t inst *2 = 0.5 m s output open 915ma i cc2 f ch = 8 mhz v cc = 3.2 v t inst *2 = 8.0 m s output open 1.5 2 ma 2.5 5.0 ma MB89P147 i ccs1 f ch = 8 mhz v cc = 5.0 v t inst *2 = 0.5 m s 37ma i ccs2 f ch = 8 mhz v cc = 3.2 v t inst *2 = 8.0 m s 1 1.5 ma i ccl subclock mode f cl = 32.768 khz v cc = 3.0 v 50 150 m a 13ma MB89P147 i ccls subclock sleep mode f cl = 32.768 khz v cc = 3.0 v 25 50 m a i cct watch mode f cl = 32.768 khz v cc = 3.0 v 315 m a i cch stop mode t a = +25 c 10 m a i a av cc f ch = 8 mhz, when a/d conversion is activated 1.5 4 ma i ah t a = +25 c, when a/d conversion is stopped 15 m a input capacitance c in other than av cc , av ss , v cc , and v ss f = 1 mhz 10 pf sleep mode
30 mb89140 series 4. ac characteristics (1) reset timing ( av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) note: t xcyl is the oscillation cycle (1/f ch ) to input to the x0 pin. (2) power-on reset (av ss = v ss = 0.0 v, t a = ?0 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. typ. max. rst ? pulse width t zlzh 16 t xcyl ns rst noise limit width t zlnc 30 50 80 ns parameter symbol condition value unit remarks min. max. power supply rising time t r 50 ms power-on reset function only power supply cut-off time t off 1 ms due to repeated operations 0.2 v cc 0.2 v cc rst t zlnc t zlzh 0.2 v 0.2 v 2.0 v 0.2 v t r v cc t off
31 mb89140 series (3) clock timing (av ss = v ss = 0.0 v, t a = ?0 c to +85 c) parameter symbol pin condition value unit remarks min. typ. max. clock frequency f ch x0, x1 2 8 mhz f cl x0a, x1a 32.768 khz clock cycle time t xcyl x0, x1 125 500 ns t lxcyl x0a, x1a 30.5 m s input clock pulse width p wh p wl x0 30 ns external clock p whl p wll x0a 15.2 m s input clock rising/falling time t cr t cf x0, x0a 10 ns external clock 0.2 v cc 0.8 v cc x0 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc x0 x1 x0 x1 when a crystal or ceramic resonator is used when an external clock is used open c0 c1 p wh p wl t xcyl x0 and x1 timing and conditions main clock conditions
32 mb89140 series (4) instruction cycle parameter symbol value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f ch , 8/f ch , 16/f ch , 64/f ch m s (4/f ch ) t inst = 0.5 m s when operating at f ch = 8 mhz 2/f cl m s t inst = 61.036 m s when operating at f cl = 32.768 khz x0a and x1a timing and conditions 0.2 v cc 0.8 v cc x0a 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc x0a x1a x0a x1a when a crystal or ceramic resonator is used when an external clock is used open x0a x1a when a crystal or ceramic resonator is used rf = approx. 2 m w c0 c1 c0 c1 r d mask rom products and MB89P147 r d rf x0a x1a when an external clock is used open mb89pv140 note: the subclock oscillator feedback resistor is connected externally in dual-clock mask rom products and in the MB89P147. (the subclock oscillator feedback resistor is connected internally in the mb89pv140-102.) t lxcyl p whl p wll subclock conditions
33 mb89140 series (5) serial i/o timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) * : for information on t inst , see ?4) instruction cycle. parameter symbol pin condition value unit remarks min. max. serial clock cycle time t scyc sck internal shift clock mode 2 t inst * m s sck so time t slov sck, so ?00 200 ns valid si sck t ivsh si, sck 1/2 t inst * m s sck valid si hold time t shix sck, si 1/2 t inst * m s serial clock ? pulse width t shsl sck external shift clock mode 1 t inst * m s serial clock ? pulse width t slsh sck 1 t inst * m s sck so time t slov sck, so 0 200 ns valid si sck t ivsh si, sck 1/2 t inst * m s sck valid si hold time t shix sck, si 1/2 t inst * m s t scyc t slov t shix t ivsh sck 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 0.8 v cc 0.3 v cc 0.8 v cc 0.3 v cc so si t slsh t slov t shix t ivsh sck 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.8 v cc 0.3 v cc 0.8 v cc 0.3 v cc so si 0.2 v cc t shsl 0.8 v cc internal shift clock mode external shift clock mode
34 mb89140 series (6) peripheral input timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) * : for information on t inst, see ?4) instruction cycle. (7) peripheral input noise limit width (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) parameter symbol pin condition value unit remarks min. max. peripheral input ? pulse width 1 t ilih1 trg, dtti adst, ec int0 to int1 ? t inst * m s peripheral input ? pulse width 1 t ihil1 trg, dtti adst, ec int0 to int1 ? t inst * m s parameter symbol condition value unit remarks min. typ. max. peripheral input ? level noise limit width 1 t ihnc1 all inputs except int1 and int0 71530ns MB89P147/pv140 15 30 60 ns except MB89P147/pv140 peripheral input ? level noise limit width 1 t ilnc1 all inputs except int1 and int0 71530ns MB89P147/pv140 15 30 60 ns except MB89P147/pv140 interrupt ? level noise limit width 2 t ihnc2 int1, int0 30 50 100 ns MB89P147/pv140 50 100 250 ns except MB89P147/pv140 interrupt ? level noise limit width 2 t ilnc2 int1, int0 30 50 100 ns MB89P147/pv140 50 100 250 ns except MB89P147/pv140 0.2 v cc 0.8 v cc t ihil1 trg dtti adst int0 to int1 ec 0.2 v cc t ilih1 p00 to p07, p01 to p17 p30 to p37, p70, p71 trg, sck, si, ec, dtti, adst int1, int0 0.8 v cc 0.2 v cc 0.8 v cc t ilnc2 0.2 v cc t ihnc2 0.8 v cc t ilnc1 t ihnc1
35 mb89140 series 5. a/d converter electrical characteristics (av cc = v cc = 5.0 v+10%, f ch = 8 mhz, av ss = v ss = 0.0 v, t a = ?0 c to +85 c) * : for information on t inst , see ?4) instruction cycle in ?. ac characteristics. notes: the smaller av cc , the greater the error would become relatively. the output impedance of the external circuit connected to an analog input block should be no more than several k w . if the output impedance is too high, the analog voltage sampling time might be insuf?ient. parameter symbol pin condition value unit remarks min. typ. max. resolution 10 bit total error av cc = v cc = 5.0 v 3.0 lsb linearity error 2.0 lsb differential linearity error 1.5 lsb zero transition voltage v ot an0 to anb av ss ?1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv full-scale transition voltage v fst an0 to anb av cc ?3.5 lsb av cc ?1.5 lsb av cc + 0.5 lsb mv interchannel disparity 4 lsb a/d mode conversion time at 8-mhz oscillation 33 t inst* analog port input current i ain an0 to anb av cc = v cc = 5.0 v 10 m a analog input voltage an0 to anb 0.0 av cc v comparator r = 3 k w c = 60 pf sample hold circuit analog channel selector r 10 k w is recommended. an when r > 10 k w , it is recommended to connect an external capacitor of approx. 0.1 ?. close for approx. 15 to 72 instruction cycles after activating a/d conversion. (the close time depends on the register settings.) . . . .
36 mb89140 series (1) a/d glossary resolution analog changes that are identi?ble with the a/d converter linearity error the deviation of the straight line connecting the zero transition point (?0 0000 0000 ?0 0000 0001? with the full-scale transition point (?1 1111 1110 ?1 1111 1111? from actual conversion characteristics differential linearity error the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value total error the difference between theoretical and actual values this error is caused by the zero transition error, full-scale transition error, linearity error, quantization error and noise. (continued) 3ff 3fe 3fd 004 003 002 001 v ot 0.5 lsb av ss 1 lsb 1.5 lsb v fst avr 3ff 3fe 3fd 004 003 002 001 v nt avr {1 lsb n + 0.5 lsb} 1 lsb = 1022 (v) v nt ?{1 lsb n + 0.5 lsb} 1 lsb digital output digital output total error for digital output n = v fst ?v ot theoretical i/o characteristics total error actual conversion value actual conversion value theoretical value analog input analog input av ss
37 mb89140 series (continued) 3ff 3fe 3fd 004 003 002 001 av ss v nt avr {1 lsb n + v ot } 1 lsb 1 lsb 004 003 002 001 av ss 3ff 3fe 3fd 3fc avr n + 1 n n ?1 n ?2 av ss avr v (n + 1) t v nt v (n + 1) t ?v nt ?1 digital output digital output digital output digital output linearity error for digital output n = differential linearity error for digital output n = v nt ?{1 lsb n + v ot } zero transition error actual conversion value actual conversion value actual conversion value actual conversion value actual conversion value actual conversion value actual conversion value actual conversion value full-scale transition error theoretical value theoretical value theoretical value analog input analog input analog input analog input v fst (measured value) v ot (measured value) linearity error differential linearity error v fst (measured value) v ot (measured value)
38 mb89140 series n example characteristics (3) ? level input voltage/? level input voltage (hysteresis input) 010 123456789 0.1 0.2 0.3 0.4 0.5 v ol (v) v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 6.0 v i ol (ma) 0.0 t a = +25? v ol vs. i ol v cc = 5.0 v 0.0 1.0 v cc ?v oh (v) v cc = 2.5 v v cc = 3.0 v v cc = 6.0 v i oh (ma) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 ?.5 ?.0 ?.5 ?.0 ?.5 ?.0 t a = +25? v cc ?v oh vs. i oh v cc = 4.0 v v cc = 5.0 v (1) ? level output voltage (2) ? level output voltage 012 3 456 7 v cc (v) 5.0 v in (v) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v ihs v ils t a = +25? cmos hysteresis input v ihs : threshold when input voltage in hysteresis characteristics is set to ? level v ils : threshold when input voltage in hysteresis characteristics is set to ? level
39 mb89140 series (4) power supply current (external clock) (continued) 2.0 3.0 4.0 5.0 6.0 7.0 16 14 12 10 8 6 4 2 0 v cc (v) f ch = 8 mhz t a = +25? divide by 4 (i cc1 ) divide by 64 (i cc2 ) i cc (ma) 2.0 3.0 4.0 5.0 6.0 7.0 4.0 3.0 2.0 1.0 0 v cc (v) i ccs (ma) i cc1 vs. v cc , i cc2 vs. v cc i ccs1 vs. v cc , i ccs2 vs. v cc 2.0 3.0 4.0 5.0 6.0 7.0 200 180 160 140 120 100 80 60 0 v cc (v) i ccl (?) 2.0 3.0 4.0 5.0 6.0 7.0 50 30 20 10 0 v cc (v) i ccls (?) i ccl vs. v cc 40 20 40 i ccls vs. v cc f ch = 8 mhz t a = +25? t a = +25? t a = +25? divide by 4 (i ccs1 ) divide by 64 (i ccs2 )
40 mb89140 series (continued) (5) pull-up resistance 2.0 3.0 4.0 5.0 6.0 7.0 16 14 12 10 8 6 4 2 0 v cc (v) i cct (?) i cct vs. v cc 18 2.0 3.0 4.0 5.0 6.0 7.0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 v cc (v) i cch (?) i cch vs. v cc 1.8 t a = +25? t a = +25? 1,000 500 100 50 10 1234567 v cc (v) r pull (k w ) t a = +85? t a = +25? t a = ?0? r pull vs. v cc
41 mb89140 series n instructions execution instructions can be divided into the following four groups: transfer arithmetic operation branch others table 1 lists symbols used for notation of instructions. table 1 instruction symbols (continued) symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits)
42 mb89140 series (continued) columns indicate the following: mnemonic: assembler notation of an instruction ~: number of instructions #: number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? indicates no change. dh is the 8 upper bits of operation description data. al and ah must become the contents of al and ah immediately before the instruction is executed. 00 becomes 00. n, z, v, c: an instruction of which the corresponding ?g will change. if + is written in this column, the relevant instruction will change its corresponding ?g. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f this indicates 48, 49, ... 4f. symbol meaning ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ? ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( ? )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
43 mb89140 series table 2 transfer instructions (48 instructions) notes: during byte transfer to a, t a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) (a) ( (ix) +off ) (a) (ext) (a) ( (ep) ) (a) (ri) (a) (a) d8 (a) (dir) (a) ( (ix) +off) (a) (ext) (a) ( (a) ) (a) ( (ep) ) (a) (ri) (dir) d8 ( (ix) +off ) d8 ( (ep) ) d8 (ri) d8 (dir) (ah),(dir + 1) (al) ( (ix) +off) (ah), ( (ix) +off + 1) (al) (ext) (ah), (ext + 1) (al) ( (ep) ) (ah),( (ep) + 1) (al) (ep) (a) (a) d16 (ah) (dir), (al) (dir + 1) (ah) ( (ix) +off), (al) ( (ix) +off + 1) (ah) (ext), (al) (ext + 1) (ah) ( (a) ), (al) ( (a) ) + 1) (ah) ( (ep) ), (al) ( (ep) + 1) (a) (ep) (ep) d16 (ix) (a) (a) (ix) (sp) (a) (a) (sp) ( (a) ) (t) ( (a) ) (th),( (a) + 1) (tl) (ix) d16 (a) (ps) (ps) (a) (sp) d16 (ah) (al) (dir): b 1 (dir): b 0 (al) (tl) ? (a) (t) (a) (ep) (a) (ix) (a) (sp) (a) (pc) al al al al al al al al al al al al al al al ah ah ah ah ah ah ah dh dh dh dh dh dh dh dh dh dh al dh dh dh dh dh ??? ??? ??? ??? ??? + + ? + + ? + + ? + + ? + + ? + + ? + + ? ??? ??? ??? ??? ??? ??? ??? ??? ??? + + ? + + ? + + ? + + ? + + ? + + ? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? + + + + ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
44 mb89140 series table 3 arithmetic operation instructions (62 instructions) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) (a) + (ri) + c (a) (a) + d8 + c (a) (a) + (dir) + c (a) (a) + ( (ix) +off) + c (a) (a) + ( (ep) ) + c (a) (a) + (t) + c (al) (al) + (tl) + c (a) (a) - (ri) - c (a) (a) - d8 - c (a) (a) - (dir) - c (a) (a) - ( (ix) +off) - c (a) (a) - ( (ep) ) - c (a) (t) - (a) - c (al) (tl) - (al) - c (ri) (ri) + 1 (ep) (ep) + 1 (ix) (ix) + 1 (a) (a) + 1 (ri) (ri) - 1 (ep) (ep) - 1 (ix) (ix) - 1 (a) (a) - 1 (a) (al) (tl) (a) (t) / (al),mod (t) (a) (a) (t) (a) (a) (t) (a) (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) (al) " (tl) (a) (al) " d8 (a) (al) " (dir) (a) (al) " ( (ep) ) (a) (al) " ( (ix) +off) (a) (al) " (ri) (a) (al) (tl) (a) (al) d8 (a) (al) (dir) dl 00 dh dh dh dh dh 00 dh dh dh + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ??? ??? + + ? + + + ??? ??? + + ? ??? ??? + + r + + r + + r + + + + + + + + + + ?+ + + ?+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r + + r + + r + + r + + r + + r + + r + + r + + r 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c a c
45 mb89140 series (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) (al) ( (ep) ) (a) (al) ( (ix) +off) (a) (al) (ri) (a) (al) (tl) (a) (al) d8 (a) (al) (dir) (a) (al) ( (ep) ) (a) (al) ( (ix) +off) (a) (al) (ri) (dir) ?d8 ( (ep) ) ?d8 ( (ix) + off) ?d8 (ri) ?d8 (sp) (sp) + 1 (sp) (sp) ?1 + + r + + r + + r + + r + + r + + r + + r + + r + + r + + + + + + + + + + + + + + + + ??? ??? 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc pc + rel if z = 0 then pc pc + rel if c = 1 then pc pc + rel if c = 0 then pc pc + rel if n = 1 then pc pc + rel if n = 0 then pc pc + rel if v " n = 1 then pc pc + rel if v " n = 0 then pc pc + rei if (dir: b) = 0 then pc pc + rel if (dir: b) = 1 then pc pc + rel (pc) (a) (pc) ext vector call subroutine call (pc) (a),(a) (pc) + 1 return from subrountine return form interrupt dh ??? ??? ??? ??? ??? ??? ??? ??? ?+ ? ?+ ? ??? ??? ??? ??? ??? ??? restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 dh ??? ??? ??? ??? ??? ???r ???s ??? ??? 40 50 41 51 00 81 91 80 90
46 mb89140 series n instruction map 0123456789 abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel l h
47 mb89140 series n mask options n ordering information no. mb89pv140 -101 mb89pv140 -102 mb89145v1 mb89146v1 mb89145v2 mb89146v2 MB89P147v1 MB89P147v2 1 power-on reset with power-on reset without power-on reset fixed to with power-on reset specify when ordering masking set with eprom programmer 2 reset pin output with reset output without reset output fixed to with power-on reset specify when ordering masking set with eprom programmer 3 clock mode selection single-clock mode dual-clock mode single clock dual clock specify when ordering masking set with eprom programmer 4 pull-up resistors p14 to p17 p32 to p37 fixed to without pull-up resistor specify when ordering masking (specify by pin) set with eprom programmer (specify by pin) 5 pull-down resistors p47 to p40 p57 to p50 p67 to p60 fixed to without pull-up resistor without pull- down resistor all pins with pull-down resistor without pull- down resistor all pins with pull-down resistor part number package remarks mb89145v1p-sh mb89145v2p-sh mb89146v1p-sh mb89146v2p-sh MB89P147v1p-sh MB89P147v2p-sh 64-pin plastic sh-dip (dip-64p-m01) mb89145v1pf mb89145v2pf mb89146v1pf mb89146v2pf MB89P147v1pf MB89P147v2pf 64-pin plastic qfp (fpt-64p-m06) mb89pv140c-101-es-sh mb89pv140c-102-es-sh 64-pin ceramic mdip (mdp-64c-p02) mb89pv140cf-101-es mb89pv140cf-102-es 64-pin ceramic mqfp (mqp-64c-p01) part number parameter
48 mb89140 series n package dimensions "a" lead no. 64 52 32 0.25(.010) 0.30(.012) 51 33 1 19 20 index typ (.016.004) 0.400.10 1.00(.0394) 0.150.05(.006.002) 18.00(.709)ref 22.300.40(.878.016) (stand off) 0.05(.002)min 3.35(.132)max (.551.008) 14.000.20 (.642.016) 16.300.40 ref 12.00(.472) (.736.016) 18.700.40 20.000.20(.787.008) 24.700.40(.972.016) (.047.008) details of "b" part 1.200.20 0 10 details of "a" part 0.18(.007)max 0.63(.025)max 0.10(.004) "b" m 0.20(.008) 1994 fujitsu limited f64013s-3c-2 c +0.50 C0 C0 +.020 C.022 +.008 C0.55 +0.22 55.118(2.170)ref index-2 15max typ 19.05(.750) (.010.002) 0.250.05 max 1.778(.070) (.070.007) 1.7780.18 1.00 .039 (.018.004) 0.450.10 0.51(.020)min 3.00(.118)min 5.65(.222)max index-1 (.669.010) 17.000.25 2.283 58.00 1994 fujitsu limited d64001s-3c-4 c dimensions in mm (inches) 64-pin plastic sh-dip (dip-64p-m01) dimensions in mm (inches) 64-pin plastic qfp (fpt-64p-m06)
49 mb89140 series +0.40 C0.20 +.016 C.008 +0.40 C0.20 +.016 C.008 1.20 .047 12.00(.472)typ (.039.010) 1.000.25 typ 18.00(.709) (.039.010) 1.000.25 (.016.004) 0.400.10 1.20 .047 (.016.004) 0.400.10 max 10.82(.426) (.006.002) 0.150.05 0.50(.020)typ 11.68(.460)typ 9.48(.373)typ 7.62(.300)typ 0.30(.012)typ (.050.005) 1.270.13 (.713.008) 18.120.20 typ 14.22(.560) typ 12.02(.473) typ 10.16(.400) typ 24.70(.972) (.878.013) 22.300.33 (.050.005) 1.270.13 typ 0.30(.012) index area 18.70(.736)typ (.642.013) 16.300.33 (.613.008) 15.580.20 1994 fujitsu limited m64004sc-1-3 c +0.13 C0.08 +.005 C.003 index area 0~9 (.750.012) 19.050.30 0.46 .018 (2.240.025) (.010.002) 0.250.05 (.050.010) 1.270.25 (.135.015) 3.430.38 55.12(2.170)ref (.035.005) 0.900.13 (.070.010) 1.7780.25 10.16(.400)max 33.02(1.300)ref (.100.010) 2.540.25 (.738.012) 18.750.30 typ 15.24(.600) 56.900.64 1994 fujitsu limited m64002sc-1-4 c 64-pin ceramic mdip (mdp-64c-p02) dimensions in mm (inches) dimensions in mm (inches) 64-pin ceramic mqfp (mqp-64c-p01)
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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